Dynamic operating conditions are commonly used to improve performance of electronic devices, including their power consumption. Reducing power consumption in electronic devices is desirable for many reasons. Reducing consumption of power lowers the heat generated by the device, thereby increasing the reliability and decreasing the operating cost of the device. In addition, reducing the consumption of power allows battery-powered portable electronic devices, such as cellular telephones, portable music players, laptop computers, and portable gaming devices, to operate for long periods without charging the batteries.
Various techniques have been devised for reducing power consumption of electronic devices. These techniques include making the chip smaller in size using Ultra Large Scale Integration (ULSI) or Very Large Scale Integration (VLSI) techniques. Power management units may also be used to reduce the power consumption. One power reduction technique includes the capability of stopping clock signals that drive circuits which are inactive in the chip for a period of time. A device employing such a technique includes a power management unit (PMU) that detects or predicts inactive circuits and accordingly stops clock signals associated with the inactive circuits. By turning off clock signals that drive inactive circuits, the power consumption of the electronic device decreases. Additionally, removing power from inactive circuits may reduce leakage currents within the circuits. Other techniques include reducing the frequency of clock signals that drive circuits during modes of operation that are not time critical and removing power from inactive circuits.
Some memories and memory controllers may not support dynamic changes in their operation to reduce power consumption using the techniques described above. As one example, memory controllers for Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) may have a delay locked loop (DLL) component that locks onto the frequency of a clock signal. If the clock is gated or the frequency is changed, the DLL may unlock, causing corruption of data during a subsequent access of memory. In order to avoid data corruption because of dynamic operating conditions, access may have to be denied for some period of time. With regard to changing the operating frequency of a memory controller for DDR DRAM, the period of time corresponds to the time required for the DLL to relock to the modified frequency.
Further complications to dynamic operating conditions are introduced by complex integrated circuitry. For example, a system-on-a-chip (SOC) may comprise multiple components that access memory, e.g., processor(s), DMA devices, camera interface, display interface, hardware accelerator, and so on. The latency and difficulty required to prevent all components from accessing the memory controller for each operating condition change may degrade performance, increase software complexity and result in inefficient, operation. DMA channels may have to be stopped and restarted, processors may be idled and latency introduced by pausing to complete pending transactions. Furthermore, SOC systems including multiprocessors may require additional software synchronization. Finally, accesses to memory components such as hardware accelerators, camera interfaces, and display interfaces on the SOC may be difficult to stop. Waiting until each component completes processing increases latency. This may greatly limit dynamically changing operating conditions to reduce power consumption.